| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | Intel Core 2 Duo |
| Model number ? | E6550 |
| CPU part numbers | HH80557PJ0534MG is an OEM/tray microprocessor BX80557E6550 is a boxed microprocessor BX80557E6550R is a boxed microprocessor |
| Frequency (MHz) ? | 2333 |
| Bus speed (MHz) ? | 1333 |
| Clock multiplier ? | 7 |
| Package | 775-land Flip-Chip Land Grid Array (FC-LGA6) 1.48" x 1.48" (3.75 cm x 3.75 cm) |
| Socket | Socket 775 (LGA775) |
| Introduction date | Jul 16, 2007 |
| Price at introduction | $163 |
| |
| S-spec numbers |
| | ES/QS processors | Production processors | | Part number | QYEN | SLA9X | | BX80557E6550 | | + | | BX80557E6550R | | + | | HH80557PJ0534MG | + | + | |
| |
| Architecture / Microarchitecture |
| Microarchitecture | Core |
| Processor core ? | Conroe |
| Core stepping ? | G0 (QYEN, SLA9X) |
| CPUID | 6FB (QYEN, SLA9X) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| Number of cores | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 32 KB instruction caches 2 x 32 KB data caches |
| Level 2 cache size ? | shared 4 MB |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- EM64T technology ?
- Virtualization Technology ?
- Execute Disable Bit technology ?
- Trusted Execution Technology
|
| Low power features | - Enhanced SpeedStep technology ?
- Stop Grant state ?
- Halt state
- Extended Halt state
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 0.85 - 1.5 |
| Minimum/Maximum operating temperature (°C) ? | 5 - 72 |
| Minimum/Maximum power dissipation (W) ? | 8 (Extended Halt mode) / 105.15 |
| Thermal Design Power (W) ? | 65 |
| |
| Notes on Intel HH80557PJ0534MG |
- Binary compatible with 32-bit x86 software
- Bus frequency is 333 MHz. Because the processor uses Quad Data Rate bus the effective bus speed is 1333 MHz
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