| General information |
| Type | CPU / Microprocessor |
| Market segment | Desktop |
| Family | AMD Phenom X4 |
| Model number ? | 9100e |
| CPU part number | HD9100OBJ4BGD is an OEM/tray microprocessor |
| Stepping codes | AAAWB AA CAAZB AA JAAWB AA |
| Frequency (MHz) ? | 1800 |
| Bus speed (MHz) ? | - 533 MHz Memory controller
- One 1600 MHz 16-bit HyperTransport link
|
| Clock multiplier ? | 9 |
| Package | 940-pin organic micro-PGA |
| Sockets | Socket AM2 Socket AM2+ |
| Weight | 1.4oz / 39.1g |
| Introduction date | Mar 27, 2008 |
| |
| Architecture / Microarchitecture |
| Microarchitecture | K10 |
| Processor core ? | Agena |
| Core stepping ? | B2 |
| CPUID | 100F22 |
| Manufacturing process | 0.065 micron SOI 450 million transistors |
| Die size | 285mm2 |
| Data width | 64 bit |
| Number of cores | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 64 KB 2-way associative instruction caches 4 x 64 KB 2-way associative data caches |
| Level 2 cache size ? | 4 x 512 KB 16-way set associative caches |
| Level 3 cache size | 2 MB 32-way set associative shared cache |
| Multiprocessing | Uniprocessor |
| Features | - MMX
- 3DNow!
- SSE
- SSE2
- SSE3
- SSE4a ?
- Advanced Bit Manipulation ?
- AMD64 technology ?
- AMD-V (virtualization) technology
- Enhanced Virus Protection ?
|
| Low power features | - Cool'n'Quiet 2.0
- CoolCore technology ?
- Independent Dynamic Core Technology ?
- Dual Dynamic Power Management ?
- Core C1 and C1E states
- Package S1, S3, S4 and S5 states
- Wideband Frequency Control
- Multi-Point Thermal Control
|
| On-chip peripherals | - Integrated dual-channel 144-bit DDR2 SDRAM Memory controller
- HyperTransport 3 technology
|
| |
| Electrical/Thermal parameters |
| V core (V) ? | 1.1 - 1.15 |
| V NorthBridge (V) | 1.15 |
| Maximum operating temperature (°C) ? | 55 - 61 |
| Thermal Design Power (W) ? | 65 |