| Architecture / Microarchitecture |
| Microarchitecture | Core |
| Processor core ? | Kentsfield |
| Core steppings ? | B0 (QMAQ) B1 (QQGV) B3 (QUPT, SL9UM) G0 (QXVD, SLACR) |
| CPUIDs | 6F4 (QMAQ) 6F7 (SL9UM) 6FB (QXVD, SLACR) |
| Manufacturing process | 0.065 micron |
| Data width | 64 bit |
| Number of cores | 4 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 4 x 32 KB instruction caches 4 x 32 KB data caches |
| Level 2 cache size ? | 2 x 4 MB caches (each L2 cache is shared between 2 cores) |
| Multiprocessing | Uniprocessor |
| Features | - MMX instruction set
- SSE
- SSE2
- SSE3
- Supplemental SSE3
- EM64T technology ?
- Virtualization Technology ?
- Execute Disable Bit technology ?
|
| Low power features | - Enhanced SpeedStep technology ?
- Stop Grant state ?
- Halt state
- Extended Halt state
|